Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Damascene (single damascene) is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In the standard dual damascene process, the insulating layer is coated with a resist material which is exposed to a first mask with the image pattern of the via openings and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled metal.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although standard dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages and problems. For example, the edges of the via openings in the lower half of the insulating layer are not only poorly defined because there are two etching steps; but also because the via edges are unprotected during the second etching. Thus, improvements are needed in the standard dual damascene process to eliminate the poor edge definition of the via openings.
Another problem associated with edge definition of the via openings is illustrated in FIG. 8. This problem is frequently encountered when an low k materials are employed in the semiconductor device. In particular, FIG. 8 shows the poor sidewall profile due to undesirable over-etching of the insulating material when the photoresist is removed or stripped. This is commonly referred to as undercutting. Undercutting is often caused when removing or stripping conventional photoresists from substrates during dual damascene processing. While the undesirable over-etching is shown in connection with the via, the same problem may occur with the trench. The over-etching leads to malformed metal vias and/or trenches as well as the trapping of air between the metal via (and/or trench) and the insulating material. This consequently degrades the electrical properties of the resultant electronic devices.
In processes where transparent layers are employed, especially in instances where transparent layers are employed over reflective layers, it is difficult to adequately pattern (for example, due to poor critical dimension control and/or undercutting). As a result, antireflection (ARC) layers may be employed. But ARCs tend to unnecessarily complicate the processing. T is therefore desirable to improve printability of photoresists while eliminating the use of ARCs.